IEEE - Institute of Electrical and Electronics Engineers, Inc. - Chip-level verification for parasitic coupling effects in deep-submicron digital designs

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings

Author(s): Lun Ye ; Foong-Charn Chang ; Feldmann, P. ; Nagaraj, N. ; Chadha, R. ; Cano, F.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: Munich, Germany, Germany
Conference Date: 9 March 1999
Page(s): 658 - 663
ISBN (Paper): 0-7695-0078-1
DOI: 10.1109/DATE.1999.761199
Regular:

Interconnect parasitics are playing a dominant role in determining chip performance and functionality in deep-submicron designs. This problem is compounded by increasing chip frequencies and... View More

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