IEEE - Institute of Electrical and Electronics Engineers, Inc. - Efficient 3D modelling for extraction of interconnect capacitances in deep submicron dense layouts

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings

Author(s): Toulouse, A. ; Bernard, D. ; Landrault, C. ; Nouet, P.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: Munich, Germany, Germany
Conference Date: 9 March 1999
Page(s): 576 - 580
ISBN (Paper): 0-7695-0078-1
DOI: 10.1109/DATE.1999.761185
Regular:

This paper introduces a set of analytical formulations for 3D modelling of inter-layer capacitances. Efficiency and accuracy are both guaranteed by the process characterization approach.... View More

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