IEEE - Institute of Electrical and Electronics Engineers, Inc. - Defect-oriented mixed-level fault simulation of digital systems-on-a-chip using HDL

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings

Author(s): Santos, M.B. ; Teixeira, J.P.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: Munich, Germany, Germany
Conference Date: 9 March 1999
Page(s): 549 - 553
ISBN (Paper): 0-7695-0078-1
DOI: 10.1109/DATE.1999.761181
Regular:

The validation of high-quality tests requires Defect-Oriented (DO) fault simulation. The purpose of this paper is to propose a methodology for mixed-level DO fault simulation, using HDL. A novel... View More

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