IEEE - Institute of Electrical and Electronics Engineers, Inc. - Digital MOS circuit partitioning with symbolic modeling

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings

Author(s): Ribas Xirgo, L. ; Carrabina Bordoll, J.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: Munich, Germany, Germany
Conference Date: 9 March 1999
Page(s): 503 - 508
ISBN (Paper): 0-7695-0078-1
DOI: 10.1109/DATE.1999.761173
Regular:

This paper presents a method to automatically recognize and model singleand multi-output logic gates out of a switch-level network, even for irregular transistor structures. Resulting subcircuit... View More

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