IEEE - Institute of Electrical and Electronics Engineers, Inc. - Efficient techniques for modeling chip-level interconnect, substrate and package parasitics

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings

Author(s): Feldmann, P. ; Kapur, S. ; Long, D.E.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: Munich, Germany, Germany
Conference Date: 9 March 1999
Page(s): 418 - 422
ISBN (Paper): 0-7695-0078-1
DOI: 10.1109/DATE.1999.761158
Regular:

Modern IC design requires accurate analysis and modeling of chip-level interconnect, the substrate and package parasitics. Traditional approaches for such analyses are computationally expensive.... View More

Advertisement