IEEE - Institute of Electrical and Electronics Engineers, Inc. - Automating the sizing of analog CMOS circuits by consideration of structural constraints

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings

Author(s): Schwencker, R. ; Eckmueller, J. ; Graeb, H. ; Antreich, K.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: Munich, Germany, Germany
Conference Date: 9 March 1999
Page(s): 323 - 327
ISBN (Paper): 0-7695-0078-1
DOI: 10.1109/DATE.1999.761141
Regular:

In this paper a method for the automatic sizing of analog integrated circuits is presented. Basic sizing rules, representing circuit knowledge, are set up before the sizing and are introduced as... View More

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