IEEE - Institute of Electrical and Electronics Engineers, Inc. - Glitch power minimization by gate freezing

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings

Author(s): Benini, L. ; De Micheli, G. ; Macii, A. ; Macii, E. ; Poncino, M. ; Scarsi, R.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: Munich, Germany, Germany
Conference Date: 9 March 1999
Page(s): 163 - 167
ISBN (Paper): 0-7695-0078-1
DOI: 10.1109/DATE.1999.761113
Regular:

This paper presents a technique for glitch power minimization in combinational circuits. The total number of glitches is reduced by replacing some existing gates with functionally equivalent ones... View More

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