IEEE - Institute of Electrical and Electronics Engineers, Inc. - A novel low power low phase-noise PLL architecture for wireless transceivers

Proceedings Ninth Great Lakes Symposium on VLSI

Author(s): Hafez, A.N. ; Elmasry, M.I.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: Ypsilanti, MI, USA, USA
Conference Date: 4 March 1999
Page(s): 306 - 309
ISBN (Paper): 0-7695-0104-4
ISSN (Paper): 1066-1395
DOI: 10.1109/GLSV.1999.757439
Regular:

A sample-and-hold stage placed in the feedback path of a PLL frequency synthesizer reduces the division ratio, and hence the phase-detector phase-noise, without the need of multiple loops, when... View More

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