IEEE - Institute of Electrical and Electronics Engineers, Inc. - A correlation matrix method of clock partitioning for sequential circuit testability

Proceedings Ninth Great Lakes Symposium on VLSI

Author(s): Yong Chang Lim ; Agrawal, V.D. ; Salnja, K.K.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: Ypsilanti, MI, USA, USA
Conference Date: 4 March 1999
Page(s): 300 - 303
ISBN (Paper): 0-7695-0104-4
ISSN (Paper): 1066-1395
DOI: 10.1109/GLSV.1999.757438
Regular:

We propose a method of partitioning the set of all flip-flops in a circuit for multiple clock testing. In the multiple clock testing, flip-flops are partitioned into different groups and each... View More

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