IEEE - Institute of Electrical and Electronics Engineers, Inc. - Symbolic multi-level verification of refinement

Proceedings Ninth Great Lakes Symposium on VLSI

Author(s): Hendricx, S. ; Claesen, L.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: Ypsilanti, MI, USA, USA
Conference Date: 4 March 1999
Page(s): 288 - 291
ISBN (Paper): 0-7695-0104-4
ISSN (Paper): 1066-1395
DOI: 10.1109/GLSV.1999.757435
Regular:

VLSI-system design can, in general, be characterized in terms of the step-wise refinement of intermediate solutions. Despite the fact that such refinements usually do not preserve time-scales,... View More

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