IEEE - Institute of Electrical and Electronics Engineers, Inc. - A test vector ordering technique for switching activity reduction during test operation

Proceedings Ninth Great Lakes Symposium on VLSI

Author(s): Girard, P. ; Guiller, L. ; Landrault, C. ; Pravossoudovitch, S.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: Ypsilanti, MI, USA, USA
Conference Date: 4 March 1999
Page(s): 24 - 27
ISBN (Paper): 0-7695-0104-4
ISSN (Paper): 1066-1395
DOI: 10.1109/GLSV.1999.757369
Regular:

This paper considers the problem of testing VLSI integrated circuits without exceeding their power ratings during test. The proposed approach is based on the reordering of test vectors of a given... View More

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