IEEE - Institute of Electrical and Electronics Engineers, Inc. - Optimal clocking and enhanced testability for high-performance self-resetting domino pipelines

Proceedings 20th Anniversary Conference on Advanced Research in VLSI

Author(s): Dooply, A.E. ; Yun, K.Y.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1999
Conference Location: Atlanta, GA, USA, USA
Conference Date: 21 March 1999
Page(s): 200 - 214
ISBN (Paper): 0-7695-0056-0
ISSN (Paper): 1522-869X
DOI: 10.1109/ARVLSI.1999.756049
Regular:

We describe a method to clock the domino pipeline at the maximum rate by using soft synchronizers between pipeline stages and thus allowing "time borrowing" i.e., allowing input signals to arrive... View More

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