IEEE - Institute of Electrical and Electronics Engineers, Inc. - An improved path enumeration method considering different fall and rise gate delays

Proceedings. XI Brazilian Symposium on Integrated Circuit Design (Cat. No.98EX216)

Author(s): Guntzel, J.L. ; Pinto, A.C.M. ; Moraes, F. ; Reis, R.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1998
Conference Location: Rio de Janeiro, Brazil, Brazil
Conference Date: 3 October 1998
Page(s): 208 - 211
ISBN (Paper): 0-8186-8704-5
DOI: 10.1109/SBCCI.1998.715443
Regular:

Most of path enumeration-based timing analysis tools use a single delay per gate for path delay calculation. However, the timing analysis of current submicron designs demands more accurate delay... View More

Advertisement