IEEE - Institute of Electrical and Electronics Engineers, Inc. - 0.5 V CMOS logic delivering 200 million 8/spl times/8 bit multiplications/s at less than 100 fJ based on a 50 nm T-gate SOI technology

Proceedings of International Symposium on Low Power Electronics and Design

Author(s): V. Dudek ; R. Grube ; B. Hofflinger ; M. Schau
Sponsor(s): ACM/SIGDA
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1998
Conference Location: Monterey, CA, USA, USA
Conference Date: 10 August 1998
Page Count: 3
Page(s): 103 - 105
ISBN (Paper): 1-58113-059-7
DOI: 10.1109/LPE.1998.708166
Regular:

High-performance CMOS logic at a very low voltage of 0.5 V can deliver 150 million 8/spl times/8 multiplications/s at an energy level of only 30fJ, if 0.35 /spl mu/m SOI technology is enhanced... View More

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