IEEE - Institute of Electrical and Electronics Engineers, Inc. - Power and performance tradeoffs using various caching strategies

Proceedings of International Symposium on Low Power Electronics and Design

Author(s): R.I. Bahar ; G. Albera ; S. Manne
Sponsor(s): ACM/SIGDA
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1998
Conference Location: Monterey, CA, USA, USA
Conference Date: 10 August 1998
Page Count: 6
Page(s): 64 - 69
ISBN (Paper): 1-58113-059-7
DOI: 10.1145/280756.295115
Regular:

In this paper, we propose several different data and instruction cache configurations and analyze their power as well as performance implications on the processor. Unlike most existing work in low... View More

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