IEEE - Institute of Electrical and Electronics Engineers, Inc. - Self-sorting radix-2 FFT on FPGAs using parallel pipelined distributed arithmetic blocks

Proceedings IEEE Symposium on FPGAs for Custom Computing Machines

Author(s): Shaditalab, M. ; Bois, G. ; Sawan, M.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1998
Conference Location: Napa Valley, CA, USA, USA
Conference Date: 17 April 1998
Page(s): 337 - 338
ISBN (Paper): 0-8186-8900-5
DOI: 10.1109/FPGA.1998.707943
Regular:

Design and implementation of parallel pipelined Fast Fourier Transform (FFT), using Decimation in Frequency (DIF) algorithm on FPGAs is presented. The FFT core for 1024 complex data point is... View More

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