IEEE - Institute of Electrical and Electronics Engineers, Inc. - A reconfigurable multiplier array for video image processing tasks, suitable for embedding in an FPGA structure

Proceedings IEEE Symposium on FPGAs for Custom Computing Machines

Author(s): Haynes, S.D. ; Cheung, P.Y.K.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1998
Conference Location: Napa Valley, CA, USA, USA
Conference Date: 17 April 1998
Page(s): 226 - 234
ISBN (Paper): 0-8186-8900-5
DOI: 10.1109/FPGA.1998.707900
Regular:

This paper presents a design for a reconfigurable multiplier array. The multiplier is constructed using an array of 4 bit Flexible Array Blocks (FABs), which could be embedded within a... View More

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