IEEE - Institute of Electrical and Electronics Engineers, Inc. - Exploiting the use of VHDL specifications in the AGENDA high-level synthesis environment

Proceedings 24th EUROMICRO Conference

Author(s): Economakos, G. ; Papakonstantinou, G.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1998
Conference Location: Vasteras, Sweden, Sweden
Conference Date: 27 August 1998
Volume: 1
ISBN (Paper): 0-8186-8646-4
ISSN (Paper): 1089-6503
DOI: 10.1109/EURMIC.1998.711782
Regular:

Recently, the AGENDA formal framework to perform high-level synthesis using attribute grammars has been presented, its main advantages being modularity and declarative notation in the development... View More

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