IEEE - Institute of Electrical and Electronics Engineers, Inc. - Bipolar process integration for a 0.25 /spl mu/m BiCMOS SRAM technology using shallow trench isolation

Proceedings of the 1997 Bipolar/BiCMOS Circuits and Technology Meeting

Author(s): Tian, H. ; Perera, A. ; Subramanian, C. ; Pham, D. ; Damiano, J. ; Scott, J. ; McNelly, T. ; Zaman, R. ; Hayden, J.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1997
Conference Location: Minneapolis, MN, USA
Conference Date: 28 September 1997
Page(s): 76 - 79
ISBN (Paper): 0-7803-3916-9
ISSN (Paper): 1088-9299
DOI: 10.1109/BIPOL.1997.647360
Regular:

This paper describes bipolar process integration issues for a 0.25 /spl mu/m BiCMOS SRAM technology which uses shallow trench isolation. In particular, we discuss: (1) minimization of arsenic... View More

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