IEEE - Institute of Electrical and Electronics Engineers, Inc. - 0.3 /spl mu/m BiCMOS technology for mixed analog/digital application systems

Proceedings of the 1997 Bipolar/BiCMOS Circuits and Technology Meeting

Author(s): Nii, H. ; Yoshino, T. ; Inoh, K. ; Itoh, N. ; Nakajima, H. ; Sugaya, H. ; Naruse, H. ; Katsumata, Y. ; Iwai, H.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1997
Conference Location: Minneapolis, MN, USA
Conference Date: 28 September 1997
Page(s): 68 - 71
ISBN (Paper): 0-7803-3916-9
ISSN (Paper): 1088-9299
DOI: 10.1109/BIPOL.1997.647358
Regular:

In this paper, 0.3 /spl mu/m BiCMOS technology for mixed analog/digital application is presented. This technology includes high f/sub max/ and high BVceo NPN transistor, 0.3 /spl mu/m CMOS, and... View More

Advertisement