IEEE - Institute of Electrical and Electronics Engineers, Inc. - Microarchitecture support for improving the performance of load target prediction

Proceedings of 30th Annual International Symposium on Microarchitecture

Author(s): Chung-Ho Chen ; Wu, A.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1997
Conference Location: Research Triangle Park, NC, USA, USA
Conference Date: 3 December 1997
Page(s): 228 - 234
ISBN (Paper): 0-8186-7977-8
ISSN (Paper): 1072-4451
DOI: 10.1109/MICRO.1997.645813
Regular:

Presents a load target prediction scheme that mitigates the impact of load latency for modern microprocessors. The scheme uses a cache-like buffer to provide the base address, offset and operand... View More

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