IEEE - Institute of Electrical and Electronics Engineers, Inc. - The multicluster architecture: reducing cycle time through partitioning

Proceedings of 30th Annual International Symposium on Microarchitecture

Author(s): Farkas, K.I. ; Chow, P. ; Jouppi, N.P. ; Vranesic, Z.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1997
Conference Location: Research Triangle Park, NC, USA, USA
Conference Date: 3 December 1997
Page(s): 149 - 159
ISBN (Paper): 0-8186-7977-8
ISSN (Paper): 1072-4451
DOI: 10.1109/MICRO.1997.645806
Regular:

The multicluster architecture that we introduce offers a decentralized, dynamically scheduled architecture, in which the register files, dispatch queue, and functional units of the architecture... View More

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