IEEE - Institute of Electrical and Electronics Engineers, Inc. - A scalable cache coherent architecture for large-scale mesh-connected multiprocessors

Proceedings of the 1997 International Symposium on Parallel Architectures, Algorithms and Networks (I-SPAN'97)

Author(s): Yunseok Rhee ; Joonwon Lee
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1997
Conference Location: Taipei, Taiwan
Conference Date: 20 December 1997
Page(s): 64 - 70
ISBN (Paper): 0-8186-8259-6
ISSN (Paper): 1087-4089
DOI: 10.1109/ISPAN.1997.645056
Regular:

Until now, various limited directory-based cache coherence protocols were proposed for medium- or large-scale multiprocessors while employing scalable directory memories. For widely shared data,... View More

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