IEEE - Institute of Electrical and Electronics Engineers, Inc. - A polynomial time algorithm for reconfiguring the 1 1/2 track-switch model with PE and bus faults

Proceedings of the 1997 International Symposium on Parallel Architectures, Algorithms and Networks (I-SPAN'97)

Author(s): Horita, T. ; Takanami, I.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1997
Conference Location: Taipei, Taiwan
Conference Date: 20 December 1997
Page(s): 16 - 22
ISBN (Paper): 0-8186-8259-6
ISSN (Paper): 1087-4089
DOI: 10.1109/ISPAN.1997.645047
Regular:

As VLSI technology has developed, the interest in implementing an entire or significant part of a parallel computer system using wafer scale integration is growing. The major problem for the case... View More

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