IEEE - Institute of Electrical and Electronics Engineers, Inc. - Low cost BIST for EDAC circuits

Proceedings Sixth Asian Test Symposium (ATS'97)

Author(s): Badura, D. ; Hlawiczka, A.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1997
Conference Location: Akita, Japan, Japan
Conference Date: 17 November 1997
Page(s): 410 - 415
ISBN (Paper): 0-8186-8209-4
ISSN (Paper): 1081-7735
DOI: 10.1109/ATS.1997.643991
Regular:

An application of new idea of designing circular self-test path (CSTP) for EDAC circuit is given in the paper. The new BIST scheme called in the paper as a condensed circular self-test path... View More

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