IEEE - Institute of Electrical and Electronics Engineers, Inc. - Accelerated test points selection method for scan-based BIST

Proceedings Sixth Asian Test Symposium (ATS'97)

Author(s): Nakao, M. ; Hatayama, K. ; Higashi, I.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1997
Conference Location: Akita, Japan, Japan
Conference Date: 17 November 1997
Page(s): 359 - 364
ISBN (Paper): 0-8186-8209-4
ISSN (Paper): 1081-7735
DOI: 10.1109/ATS.1997.643983
Regular:

This paper presents an accelerated test points selection method for circuits designed by a full-scan based BIST scheme. In order to speed up the test points selection method based on cost... View More

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