IEEE - Institute of Electrical and Electronics Engineers, Inc. - On chip weighted random patterns

Proceedings Sixth Asian Test Symposium (ATS'97)

Author(s): Savir, J.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1997
Conference Location: Akita, Japan, Japan
Conference Date: 17 November 1997
Page(s): 344 - 352
ISBN (Paper): 0-8186-8209-4
ISSN (Paper): 1081-7735
DOI: 10.1109/ATS.1997.643981
Regular:

This paper describes the design details, operation, cost, and performance of a distributed weighted pattern test approach at the chip level. The traditional LSSD SRLs are being replaced by WRP... View More

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