IEEE - Institute of Electrical and Electronics Engineers, Inc. - Design of delay-verifiable combinational logic by adding extra inputs

Proceedings Sixth Asian Test Symposium (ATS'97)

Author(s): Xiaoming Yu ; Yinghua Min
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1997
Conference Location: Akita, Japan, Japan
Conference Date: 17 November 1997
Page(s): 332 - 336
ISBN (Paper): 0-8186-8209-4
ISSN (Paper): 1081-7735
DOI: 10.1109/ATS.1997.643979
Regular:

Correct operation of logic circuits requires not only the functional correctness, but also the correctness of temporal behavior. This paper deals with the problem of delay testability of two-level... View More

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