IEEE - Institute of Electrical and Electronics Engineers, Inc. - Memory efficient ATPG for path delay faults

Proceedings Sixth Asian Test Symposium (ATS'97)

Author(s): Wangning Long ; Zhongchen Li ; Shiyuan Yang ; Yinghua Min
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1997
Conference Location: Akita, Japan, Japan
Conference Date: 17 November 1997
Page(s): 326 - 331
ISBN (Paper): 0-8186-8209-4
ISSN (Paper): 1081-7735
DOI: 10.1109/ATS.1997.643978
Regular:

A memory efficient test pattern generator for path delay faults, DTPG, is presented in this paper, which uses the efficient path identifier to represent a path. A compact bit table, path... View More

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