IEEE - Institute of Electrical and Electronics Engineers, Inc. - A method of generating tests for marginal delays and delay faults in combinational circuits

Proceedings Sixth Asian Test Symposium (ATS'97)

Author(s): Takahashi, H. ; Matsunaga, T. ; Boateng, K.O. ; Takamatsu, Y.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1997
Conference Location: Akita, Japan, Japan
Conference Date: 17 November 1997
Page(s): 320 - 325
ISBN (Paper): 0-8186-8209-4
ISSN (Paper): 1081-7735
DOI: 10.1109/ATS.1997.643977
Regular:

In this paper, we propose an algorithmic method for generating a test for marginal delays and gate delay faults, called an MD test. The time at which the MD test activates the latest transition at... View More

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