IEEE - Institute of Electrical and Electronics Engineers, Inc. - Test pattern and test configuration generation methodology for the logic of RAM-based FPGA

Proceedings Sixth Asian Test Symposium (ATS'97)

Author(s): Renovell, M. ; Portal, J.M. ; Figueras, J. ; Zorian, Y.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1997
Conference Location: Akita, Japan, Japan
Conference Date: 17 November 1997
Page(s): 254 - 259
ISBN (Paper): 0-8186-8209-4
ISSN (Paper): 1081-7735
DOI: 10.1109/ATS.1997.643967
Regular:

The test of the Configurable Logic Blocks of RAM based FPGAs under a Stuck-At fault model has been studied. The high cost of changing the configuration, by reprogramming the FPGA during testing,... View More

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