IEEE - Institute of Electrical and Electronics Engineers, Inc. - Testing for the programming circuit of LUT-based FPGAs

Proceedings Sixth Asian Test Symposium (ATS'97)

Author(s): Michinishi, H. ; Yokohira, T. ; Okamoto, T. ; Inoue, T. ; Fujiwara, H.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1997
Conference Location: Akita, Japan, Japan
Conference Date: 17 November 1997
Page(s): 242 - 247
ISBN (Paper): 0-8186-8209-4
ISSN (Paper): 1081-7735
DOI: 10.1109/ATS.1997.643965
Regular:

The programming circuit of look-up table based FPGAs consists of two shift registers, a control circuit and a configuration memory (SRAM) cell array. Because the configuration memory cell array... View More

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