IEEE - Institute of Electrical and Electronics Engineers, Inc. - Application of a design for delay testability approach to high speed logic LSIs

Proceedings Sixth Asian Test Symposium (ATS'97)

Author(s): Hatayama, K. ; Ikeda, M. ; Takakura, M. ; Uchiyama, S. ; Sakamoto, Y.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1997
Conference Location: Akita, Japan, Japan
Conference Date: 17 November 1997
Page(s): 112 - 115
ISBN (Paper): 0-8186-8209-4
ISSN (Paper): 1081-7735
DOI: 10.1109/ATS.1997.643944
Regular:

This paper presents a design for delay testability approach to improve delay fault coverage for high speed logic LSIs. In order to simplify the model for delay test generation from two stage... View More

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