IEEE - Institute of Electrical and Electronics Engineers, Inc. - Test generation for stuck-on faults in BDD-based pass-transistor logic SPL

Proceedings Sixth Asian Test Symposium (ATS'97)

Author(s): Shinogi, T. ; Hayashi, T. ; Taki, K.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1997
Conference Location: Akita, Japan, Japan
Conference Date: 17 November 1997
Page(s): 16 - 21
ISBN (Paper): 0-8186-8209-4
ISSN (Paper): 1081-7735
DOI: 10.1109/ATS.1997.643908
Regular:

This paper presents a method of test generation for stuck-on faults in a pass-transistor logic SPL by logic testing. We describe how to create a discrepancy using a pre-computed table for voltage... View More

Advertisement