IEEE - Institute of Electrical and Electronics Engineers, Inc. - New layout design for submicron CMOS output transistors to improve driving capability and ESD robustness in per unit layout area

Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits

Author(s): Ming-Dou Ker ; Tung-Yang Chen ; Chung-Yu Wu
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1997
Conference Location: Singapore
Conference Date: 25 July 1997
Page(s): 103 - 108
ISBN (Paper): 0-7803-3985-1
DOI: 10.1109/IPFA.1997.638152
Regular:

Three new device structures to effectively reduce the layout area of CMOS output buffers with higher driving capability and better ESD reliability are proposed. With theoretical calculation and... View More

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