IEEE - Institute of Electrical and Electronics Engineers, Inc. - Functional failure analysis of logic LSIs from backside of the chip and its verification by logic simulation

Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits

Author(s): Ishii, T. ; Inoue, M. ; Asatani, N. ; Naitoh, K. ; Mitsuhashi, J.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1997
Conference Location: Singapore
Conference Date: 25 July 1997
Page(s): 27 - 32
ISBN (Paper): 0-7803-3985-1
DOI: 10.1109/IPFA.1997.638068
Regular:

A novel technique has been developed for fault isolation in logic LSIs. The technique is constructed using backside infra-red light detection through the silicon chip by an emission microscope,... View More

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