IEEE - Institute of Electrical and Electronics Engineers, Inc. - Algorithms for switch level delay fault simulation

Proceedings International Test Conference 1997

Author(s): Bose, S. ; Agrawal, V.D. ; Szymanski, T.G.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1997
Conference Location: Washington, DC, USA, USA
Conference Date: 6 November 1997
Page(s): 982 - 991
ISBN (Paper): 0-7803-4209-7
ISSN (Paper): 1089-3539
DOI: 10.1109/TEST.1997.639714
Regular:

Delay test problems are well understood for gate level circuits. For certain logic families, delays depend on the charge stored at internal nodes. For such circuits, gate level models do not... View More

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