IEEE - Institute of Electrical and Electronics Engineers, Inc. - A new validation methodology combining test and formal verification for PowerPC/sup TM/ microprocessor arrays

Proceedings International Test Conference 1997

Author(s): Wang, L.C. ; Abadir, M.S.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1997
Conference Location: Washington, DC, USA, USA
Conference Date: 6 November 1997
Page(s): 954 - 963
ISBN (Paper): 0-7803-4209-7
ISSN (Paper): 1089-3539
DOI: 10.1109/TEST.1997.639711
Regular:

Test and validation of embedded array blocks remain as a major challenge in today's processor design environment. The difficulty comes from two folds. First, the sizes of the arrays are too large... View More

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