IEEE - Institute of Electrical and Electronics Engineers, Inc. - On-line testable logic design for FPGA implementation

Proceedings International Test Conference 1997

Author(s): Burress, A.L. ; Lala, P.K.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1997
Conference Location: Washington, DC, USA, USA
Conference Date: 6 November 1997
Page(s): 471 - 478
ISBN (Paper): 0-7803-4209-7
ISSN (Paper): 1089-3539
DOI: 10.1109/TEST.1997.639653
Regular:

In recent years, a number of logic design techniques for look-up table (LUT) based FPGAs have been proposed. However, none of these address issues such as fault detection or testability. This... View More

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