IEEE - Institute of Electrical and Electronics Engineers, Inc. - Delay testing with clock control: an alternative to enhanced scan

Proceedings International Test Conference 1997

Author(s): Tekumalla, R.C. ; Menon, P.R.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1997
Conference Location: Washington, DC, USA, USA
Conference Date: 6 November 1997
Page(s): 454 - 462
ISBN (Paper): 0-7803-4209-7
ISSN (Paper): 1089-3539
DOI: 10.1109/TEST.1997.639651
Regular:

Path delay fault testing in non-scan sequential circuits is complicated by the limited state transitions during normal operation. An accepted method for overcoming this difficulty is to use a scan... View More

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