IEEE - Institute of Electrical and Electronics Engineers, Inc. - Scan latch design for delay test

Proceedings International Test Conference 1997

Author(s): Savir, J.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1997
Conference Location: Washington, DC, USA, USA
Conference Date: 6 November 1997
Page(s): 446 - 453
ISBN (Paper): 0-7803-4209-7
ISSN (Paper): 1089-3539
DOI: 10.1109/TEST.1997.639650
Regular:

This paper describes three new designs of a shift register latch that lend themselves to distributed self-test and delay test. The advantages of these new SRLs are faster application of test... View More

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