IEEE - Institute of Electrical and Electronics Engineers, Inc. - Compact signed-digit adder using multiple-valued logic

Proceedings Seventeenth Conference on Advanced Research in VLSI

Author(s): Gonzalez, A.F. ; Mazumder, P.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1997
Conference Location: Ann Arbor, MI, USA, USA
Conference Date: 15 September 1997
Page(s): 96 - 113
ISBN (Paper): 0-8186-7913-1
DOI: 10.1109/ARVLSI.1997.634849
Regular:

As minimum feature sizes shrink and the number of transistors integrated in a single chip grow, interconnect complexity is one of the most important issues to be solved in future VLSI chips. The... View More

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