IEEE - Institute of Electrical and Electronics Engineers, Inc. - A new SRAM cell design using 0.35 /spl mu/m CMOS/SIMOX technology

1997 IEEE International SOI Conference Proceedings

Author(s): Kumagai, K. ; Yamada, T. ; Iwaki, H. ; Nakamura, H. ; Onishi, H. ; Matsubara, Y. ; Imai, K. ; Kurosawa, S.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1997
Conference Location: Fish Camp, CA, USA, USA
Conference Date: 6 October 1997
Page(s): 174 - 175
ISBN (Paper): 0-7803-3938-X
ISSN (Paper): 1078-621X
DOI: 10.1109/SOI.1997.634989
Regular:

In SOI/CMOS devices, it is known that the integration density and the circuit performance can be improved using a layout of abutted n/sup +/ and p/sup +/ drain regions. Utilizing these advantages... View More

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