IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 0.35 /spl mu/m 560 KG SOI/CMOS gate array using field-shield isolation technique

1997 IEEE International SOI Conference Proceedings

Author(s): Mashiko, K. ; Ueda, K. ; Nii, K. ; Wada, Y. ; Hirota, T. ; Maeda, S. ; Iwamatsu, T. ; Yamaguchi, Y. ; Ipposhi, T. ; Maegawa, S. ; Hamano, H.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1997
Conference Location: Fish Camp, CA, USA, USA
Conference Date: 6 October 1997
Page(s): 166 - 167
ISBN (Paper): 0-7803-3938-X
ISSN (Paper): 1078-621X
DOI: 10.1109/SOI.1997.634985
Regular:

Summary form only given. SOI/CMOS devices have been developed not only for memory LSIs but also for logic LSIs. Some of the recent works include gate arrays having 220-320 K usable gates and... View More

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