IEEE - Institute of Electrical and Electronics Engineers, Inc. - High performance dual-gate FD-SOI CMOS process with an ultra thin TiSi/sub 2/

1997 IEEE International SOI Conference Proceedings

Author(s): Nakamura, I. ; Imai, K. ; Onishi, H. ; Kumagai, K. ; Yamada, T. ; Iwaki, K. ; Matsubara, Y. ; Ishigami, T. ; Furosawa, S. ; Horiuchi, T.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1997
Conference Location: Fish Camp, CA, USA, USA
Conference Date: 6 October 1997
Page(s): 24 - 25
ISBN (Paper): 0-7803-3938-X
ISSN (Paper): 1078-621X
DOI: 10.1109/SOI.1997.634914
Regular:

Summary form only given. We have developed a manufacturable FD-SOI 0.35 /spl mu/m CMOS process with an ultra thin TiSi/sub 2/ film. We obtained sheet resistance of 10 /spl Omega//sq. for N/sup +/... View More

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