IEEE - Institute of Electrical and Electronics Engineers, Inc. - Salicide process for 400 /spl Aring/ fully-depleted SOI-MOSFETs using NiSi

1997 IEEE International SOI Conference Proceedings

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Summary form only given. The salicide process is a well-known technique to reduce source/drain and gate resistances of SOI-MOSFETs. However, it is becoming increasingly difficult to implement as the Si layer thickness is scaled to less than 500 /spl Aring/. The amount of Si that can be consumed during the salicide process should be less than the thickness of the Si layer. Once the Si consumption exceeds the amount of the Si layer, voids occur at the silicide/silicon interface beneath the oxide spacers and the silicide encroaches laterally beneath the spacer. It is important to form a thermally stable thin silicide only a few hundred /spl Aring/ thick. In this paper, we demonstrate that Ni is a very suitable candidate for a salicide process on very thin (400 /spl Aring/) fully-depleted SOI-MOSFETs. Source/drain resistances of NMOS and PMOS transistors on SIMOX substrates with values of 500 /spl Omega/-/spl mu/m and 800 /spl Omega/-/spl mu/m have been achieved, which are among the best values ever reported. We also have theoretically evaluated the thermal effects of the salicide process.

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Author(s):	Deng, F. ; Johnson, R.A. ; Dubbelday, W.B. ; Garcia, G.A. ; Asbeck, P.M. ; Lau, S.S.
Publisher:	IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date:	1 January 1997
Conference Location:	Fish Camp, CA, USA, USA
Conference Date:	6 October 1997
Page(s):	22 - 23
ISBN (Paper):	0-7803-3938-X
ISSN (Paper):	1078-621X
DOI:	10.1109/SOI.1997.634913