IEEE - Institute of Electrical and Electronics Engineers, Inc. - Salicide process for 400 /spl Aring/ fully-depleted SOI-MOSFETs using NiSi

1997 IEEE International SOI Conference Proceedings

Author(s): Deng, F. ; Johnson, R.A. ; Dubbelday, W.B. ; Garcia, G.A. ; Asbeck, P.M. ; Lau, S.S.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1997
Conference Location: Fish Camp, CA, USA, USA
Conference Date: 6 October 1997
Page(s): 22 - 23
ISBN (Paper): 0-7803-3938-X
ISSN (Paper): 1078-621X
DOI: 10.1109/SOI.1997.634913
Regular:

Summary form only given. The salicide process is a well-known technique to reduce source/drain and gate resistances of SOI-MOSFETs. However, it is becoming increasingly difficult to implement as... View More

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