IEEE - Institute of Electrical and Electronics Engineers, Inc. - Simultaneous multithreaded vector architecture: merging ILP and DLP for high performance

Proceedings Fourth International Conference on High-Performance Computing

Author(s): Espasa, R. ; Valero, M.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1997
Conference Location: Bangalore, India, India
Conference Date: 18 December 1997
Page(s): 350 - 357
ISBN (Paper): 0-8186-8067-9
DOI: 10.1109/HIPC.1997.634514
Regular:

Shows that instruction-level parallelism (ILP) and data-level parallelism (DLP) can be merged in a single simultaneous vector multithreaded architecture to execute regular vectorizable code at a... View More

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