IEEE - Institute of Electrical and Electronics Engineers, Inc. - Fast multiplier schemes using large parallel counters and shift switches

Proceedings Fourth International Conference on High-Performance Computing

Author(s): Rong Lin
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1997
Conference Location: Bangalore, India, India
Conference Date: 18 December 1997
Page(s): 302 - 308
ISBN (Paper): 0-8186-8067-9
DOI: 10.1109/HIPC.1997.634507
Regular:

We present novel fast parallel multiplier schemes. In contrast to the full adder binary logic based traditional designs, we use (incomplete) large parallel counters and large shift switch... View More

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