IEEE - Institute of Electrical and Electronics Engineers, Inc. - 3D Global Interconnect Parameter ExtractoR for full-chip global critical path analysis

Electrical Performance of Electronic Packaging

Author(s): Oh, S.Y. ; Okasaki, K. ; Moll, J. ; Nakagawa, O.S. ; Chang, N.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1997
Conference Location: San Jose, CA, USA, USA
Conference Date: 27 October 1997
Page(s): 46 - 49
ISBN (Paper): 0-7803-8649-3
DOI: 10.1109/EPEP.1997.634036
Regular:

A 3D Global Interconnect Parameter ExtractoR (GIPER) has been developed to provide a practical extraction tool for the full-chip global critical path analysis. It extracts the interconnect... View More

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