IEEE - Institute of Electrical and Electronics Engineers, Inc. - Improving the accuracy of on-chip parasitic extraction

Electrical Performance of Electronic Packaging

Author(s): Ching-Chao Huang ; Kyung Suk Oh ; Shun-Lien Wang ; Panchapakesan, S.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 1997
Conference Location: San Jose, CA, USA, USA
Conference Date: 27 October 1997
Page(s): 42 - 45
ISBN (Paper): 0-7803-8649-3
DOI: 10.1109/EPEP.1997.634035
Regular:

The rule-based layout parameter extraction (LPE) tools are most often used to extract the full-chip parasitics, but their accuracy strongly depends on how the capacitance models are specified.... View More

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